This invention relates to the use of semiconductor memory devices for storing information in digital form, and more particularly to the problems encountered when MOS memory devices are used at high speed for the storage of television signals in digital form. In recent years, large scale integrated circuits have become available incorporating arrays of MOS transistors so as to form large numbers of memory cells.
In certain kinds of these storage devices, one or more terminals of each memory cell are connected together so that a common control is provided to a portion of the memory. The result of this common connection to a multiplicity of memory cells is that the device presents the total capacitive load at the control input, and a suitable drive amplifier must be provided to supply the necessary charging currents.
High speed MOS memory devices often employ demultiplexing techniques within the integrated circuit so as to enhance their performance, and more than one phase of control signal is then required. The integrated circuit MOS shift register is a device in this category, and two phase clocking of the digital information through the serially connected memory cells is a common practice. In this case, two drive amplifiers would provide the alternate charging currents to the two phase clock inputs of the device.
A problem arises however, in that a significant amount of capacitive cross coupling exists between the two phase clock inputs of the integrated circuit which interacts with the input capacitance of each phase. These capacitances effectively form a capacitive divider dependent on the ratio of the cross coupling capacitance to the input capacitance. This divider impresses an unwanted proportion of each clock drive waveform on to the other clock input. This impression of unwanted portions of the signals one on another is known as cross-talk and appears as transients on the input waveforms.
If clock drive amplifiers can be selected for operating the storage device which present driving impedances which are sufficiently low, then the capacitive cross-talk will be reduced. However, commercially available clock drive amplifiers do not satisfy this requirement and the amount of cross-talk which occurs between the clocking waveforms can far exceed the permissible operating limits of the MOS storage device. Maloperation in this way can lead to loss of stored data and/or damage to the storage device.